1. Field of the Invention
The present invention relates to a semiconductor integrated circuit testing apparatus for testing various kinds of semiconductor integrated circuits (a semiconductor integrated circuit will be hereinafter referred to as IC) and a composite semiconductor integrated circuit testing apparatus that is constructed such that a plurality of semiconductor integrated circuit testing apparatus of such type are combined so as to be able to test a large scale integrated circuit (LSI), particularly a large scale integrated circuit having many pins.
2. Description of the Related Art
As is well known, in this technical field, a semiconductor integrated circuit (hereinafter referred to as IC) in which a logic circuit portion (logic portion) is dominant is called "logic IC", and a semiconductor integrated circuit in which a memory portion is dominant is called "memory IC". In addition, an IC in which a logic portion and a memory portion are present in mixture on one chip is called "System LSI" (Systematic Large Scale Integrated Circuit), "System On Chip" (SOC) or the like.
FIG. 4 shows, in outline, a configuration of the general IC testing apparatus (hereinafter referred to as an IC tester) that has conventionally been used. The illustrated IC tester comprises an IC tester proper 100 and a test head 200. The IC tester proper 100 comprises, in this example, a controller 101, a timing generator 102, a pattern generator 103, a waveform formatter 104, a driver 105, a comparator 106, a logical comparator 107, a failure analysis memory 108 and a voltage generator 109.
The test head 200 is constructed separately from the IC tester proper 100, and usually has a predetermined number of IC sockets (not shown) mounted on its top portion. In addition, within the test head 200 is accommodated a printed board called "pin card" in this technical field. A circuit containing the driver 105 and the comparator 106 of the IC tester proper 100 is usually formed on the pin card. In general, the test head 200 is mounted to a test section of an IC transporting and handling apparatus called "handler" in this technical field. The test head 200 is electrically connected to the IC tester proper 100 by signal transmission means such as cables, optical fibers or the like.
An IC to be tested (IC under test) 300 is mounted on an IC socket on the test head 200, through which a test pattern signal is applied to the IC under test (generally referred to as DUT) 300 from the IC tester proper 100 as well as a response signal from the IC under test 300 is supplied to the IC tester proper 100 in order to test and measure the IC under test 300.
The controller 101 is constituted by a computer system, in which a test program created by a user (programmer) is stored, and the entire IC tester is controlled in accordance with the test program. As can be easily understood by referring to FIG. 5, the controller 101 is connected to the timing generator 102, the pattern generator 103, the waveform formatter 104, the logical comparator 107, the failure analysis memory 108, the voltage generator 109, and the like via a tester bus 111. These timing generator 102, pattern generator 103, waveform formatter 104, logical comparator 107, failure analysis memory 108, voltage generator 109, and the like operate as terminal devices and carry out a test for the IC under test 300 in accordance with control instructions or commands outputted from the controller 101.
A test, for example, a functional test for the IC under test is performed as follows.
A pattern generating sequence described in the test program stored in the controller 101 is previously stored in the pattern generator 103 prior to the start of a test. When a test start instruction is given thereto from the controller 101, the pattern generator 103 outputs test pattern data to be applied to the IC under test 300 in accordance with the stored pattern generating sequence. As the pattern generator 103, an ALPG (Algorithmic Pattern Generator) is generally used. The ALPG is a pattern generator that generates a test pattern to be applied to a semiconductor device (for example, an IC) by an arithmetic and logic operation or computation using internal registers each having an arithmetic and logic function or computing function.
Timing generator 102 has timing data previously stored therein prior to the start of a test, the timing data being described in the test program stored in the controller 101 and outputted for every test period. The timing generator 102 outputs a clock pulse for each test period in accordance with the stored timing data. This clock pulse is supplied to the waveform formatter 104, the logical comparator 107 and the like.
The waveform formatter 104 defines a rise timing and a fall timing of a logical waveform, based on the test pattern data outputted from the pattern generator 103 and the clock pulse outputted from the timing generator 102, to produce a test pattern signal having a real waveform that changes from/to logical H (logical "1") to/from logical L (logical "0"). This test pattern signal is applied to the IC under test 300 via the driver 105.
The driver 105 defines the amplitude of the test pattern signal outputted from the waveform formatter 104 to a desired amplitude (logical H, i.e., voltage VIH of logical "1" and logical L, i.e., voltage VIL of logical "0") and applies such test pattern signal to the IC socket of the test head 200, thereby to drive the IC under test 300.
The comparator 106 determines whether or not a logical value of a response signal outputted from the IC under test 300 has a normal voltage value. That is, the comparator 106 determines whether or not a voltage of logical H has a value equal to or greater than a defined voltage value VOH and whether or not a voltage of logical L has a value equal to or less than a defined voltage value VOL. In the case that the determination result indicates a failure, the comparator 106 outputs a signal of logical H (logical "1") indicating the failure.
An output signal based on the determination result of the comparator 106 is supplied to the logical comparator 107 where the output signal is compared with an expected value pattern data supplied from the pattern generator 103 to determine whether or not the IC under test 300 has outputted a normal response signal.
The comparison result of the logical comparator 107 is taken in the failure analysis memory 108. In the case that a failure has occurred, the test pattern address of the failure, the output logical data of the failure pin of the IC under test 300, and the expected value pattern data at that time are stored in the failure analysis memory 108, and these data are utilized for an evaluation of the LSI after the completion of the test.
The voltage generator 109 generates amplitude voltages VIH and VIL to be applied to the driver 105, and comparison voltages VOH and VOL to be applied to the comparator 106, in accordance with a set value being sent from the controller 101. As a result, there is generated from the driver 105 a driving signal having an amplitude value which fulfills the standard of the IC under test 300. In addition, the comparator 106 can determine whether or not the response signal from the IC under test 300 has a logical value of the voltage fulfilling the standard of the IC under test 300.
FIG. 4 is illustrated such that a test pattern signal outputted from the driver 105 is applied to only one pin of the IC under test 300 and that a response signal from that one pin of the IC under test 300 is supplied to the comparator 106. However, in practice, a predetermined number, for example, 512 of drivers 105 are provided, and also the same predetermined number (512) of comparators 106 as that of the drivers 105 are provided. In FIG. 5, in order to simplify the figure, each of the components (the controller 101, the timing generator 102, the pattern generator 103, the waveform formatter 104, the logical comparator 107, the failure analysis memory 108 and the voltage generator 109) except the drivers 105 and the comparators 106 is shown as one block, but in reality the remaining components except the controller 101 and the timing generator 102 are also provided by the same number (512) as that of the drivers 105, respectively. That is, only the controller 101 and the timing generator 102 are used in common to each of the pins of the IC under test 300.
As mentioned above, since the circuit containing the drivers 105 and the comparators 106 of the IC tester proper 100 is usually accommodated in the test head 200, in practice, the waveform formatter 104 and the logical comparator 107 of the IC tester proper 100 are electrically connected to the drivers 105 and the comparators 106 within the test head 200 by signal transmission paths or lines such as, for example, 512 cables, 512 optical fibers or the like.
For example, in the case that the illustrated IC tester is provided with 512 drivers 105 and 512 comparators 106, if the number of pins of the IC under test 300 shown in FIG. 4 is equal to or less than 512, all of the pins are connected to the output terminals of the corresponding drivers and the input terminals of the corresponding comparators through the IC socket, respectively. In general, a signal transmission path or line connecting between the IC tester proper 100 and the test head 200 is called "channel", and the number of signal transmission paths or lines is called "the number of channels".
As discussed above, the timing generator 102, the pattern generator 103, the waveform formatter 104, the logical comparator 107, the failure analysis memory 108 and the voltage generator 109 shown in FIG. 4 are treated as terminal devices connected to the tester bus 111. Therefore, if the entire configuration of the IC tester proper 100 shown in FIG. 4 is depicted in a hierarchical structure, it is as shown in FIG. 5. Further, although the IC tester proper 100 is shown as one block, the IC tester proper 100 comprises a plurality of, for example, 512 pattern generators 103, 512 waveform formatters 104, 512 logical comparators 107, 512 failure analysis memories 108, and 512 voltage generators 109. In addition, 512 drivers 105 and 512 comparators 106 shown within the IC tester proper 100 are usually accommodated within the test head 200, and the waveform formatters 104 and the logical comparators 107 are electrically connected to the drivers 105 and the comparators 106 by 512 signal transmission paths, respectively. Consequently, this IC tester is provided with 512 channels.
As can be understood from FIG. 5, the maximum number of pins of the IC under test 300 that can be tested by the conventional IC tester is mainly determined by the number of the waveform formatters 104 and the number of the logical comparators 107, that is, the number of channels that the IC tester is provided with. Therefore, it is impossible to test an IC having its pins the number of which exceeds the number of channels of the IC tester. In other words, the maximum number of pins that can be tested has been limited to a finite value that is the same as the number of waveform formatters 104 and the number of logical comparators 107 provided in the IC tester proper 100, for example, 512 pins.
On the contrary, in current circumstances, the number of kinds or types of ICs tends to increase, and the scale (the density of integration) thereof also tends to be expanding. Particularly, in the case of an IC in which a logic portion and a memory portion are present in mixture on one chip (a logic/memory mixed IC), it has a multiplicity of pins such as of the order of 1300 pins in total resulting from 1200 pins or so for the logic portion and 100 pins or so for the memory portion, for instance.
In the case of testing such IC having many pins as mentioned above, an IC tester especially developed for an IC having many pins is needed. Currently, there is available an IC tester that can test an IC the number of pins of which is approximately 1300 or so. However, there is a serious drawback that such IC tester is extremely expensive, and the economical burden on a user is very large.